Cryogen-free operation of is essential to spread applications of superconductivity and is indeed unavoidable in some cases. In electrical metrology applications, higher temperature operation to reduce the refrigerator size and complexity is not yet possible, since arrays of Josephson junctions for voltage standard applications made with high-temperature superconductors are not yet available. The superconductor-normal metal-insulator-superconductor (SNIS) technology developed at INRIM uses low temperature superconductors, but allows operation well above liquid helium temperature. It is thus interesting for application to a compact cryocooled standard. We studied SNIS devices cooled with a closed-cycle refrigerator, both in DC and under RF irradiation. Issues related to thermal design of the apparatus are analyzed. The dependence of RF steps on the number of junctions observed is discussed in detail and interpreted as a consequence of power dissipated inside the chip.
Titolo: | Tests of SNIS Josephson Arrays Cryocooler Operation |
Autori: | |
Data di pubblicazione: | 2015 |
Rivista: | |
Abstract: | Cryogen-free operation of is essential to spread applications of superconductivity and is indeed unavoidable in some cases. In electrical metrology applications, higher temperature operation to reduce the refrigerator size and complexity is not yet possible, since arrays of Josephson junctions for voltage standard applications made with high-temperature superconductors are not yet available. The superconductor-normal metal-insulator-superconductor (SNIS) technology developed at INRIM uses low temperature superconductors, but allows operation well above liquid helium temperature. It is thus interesting for application to a compact cryocooled standard. We studied SNIS devices cooled with a closed-cycle refrigerator, both in DC and under RF irradiation. Issues related to thermal design of the apparatus are analyzed. The dependence of RF steps on the number of junctions observed is discussed in detail and interpreted as a consequence of power dissipated inside the chip. |
Handle: | http://hdl.handle.net/11696/33300 |
Appare nelle tipologie: | 1.1 Articolo in rivista |
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