Measurements of fractional multiples of the v = 2 plateau quantized Hall resistance (R ≈ 12 906 Ω) were enabled by the utilization of multiple current terminals on millimetre-scale graphene p–n junction (pnJ) devices fabricated with interfaces along both lateral directions. These quantum Hall resistance checkerboard devices have been demonstrated to match quantized resistance outputs numerically calculated with the LTspice circuit simulator. From the devices' functionality, more complex embodiments of the quantum Hall resistance checkerboard were simulated to highlight the parameter space within which these devices could operate. Moreover, these measurements suggest that the scalability of pnJ fabrication on millimetre or centimetre scales is feasible with regards to graphene device manufacturing by using the far more efficient process of standard ultraviolet lithography.

Development of gateless quantum Hall checkerboard p–n junction devices / Patel, Dinesh K; Marzano, Martina; Liu, Chieh-I; Kruskopf, Mattias; Elmquist, Randolph E; Liang, Chi-Te; Rigosi, Albert F. - In: JOURNAL OF PHYSICS D. APPLIED PHYSICS. - ISSN 0022-3727. - 53:34(2020), p. 345302. [10.1088/1361-6463/ab8d6f]

Development of gateless quantum Hall checkerboard p–n junction devices

Marzano, Martina;
2020

Abstract

Measurements of fractional multiples of the v = 2 plateau quantized Hall resistance (R ≈ 12 906 Ω) were enabled by the utilization of multiple current terminals on millimetre-scale graphene p–n junction (pnJ) devices fabricated with interfaces along both lateral directions. These quantum Hall resistance checkerboard devices have been demonstrated to match quantized resistance outputs numerically calculated with the LTspice circuit simulator. From the devices' functionality, more complex embodiments of the quantum Hall resistance checkerboard were simulated to highlight the parameter space within which these devices could operate. Moreover, these measurements suggest that the scalability of pnJ fabrication on millimetre or centimetre scales is feasible with regards to graphene device manufacturing by using the far more efficient process of standard ultraviolet lithography.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11696/64705
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