Phase Noise and Frequency Stability of the Red-Pitaya Internal PLL

In field-programmable gate array platforms, the main clock is generally a low-cost quartz oscillator whose stability is of the order of 10-9 to 10-10 in the short term and 10-7 to 10-8 in the medium term, with the uncertainty of tens of ppm. Better stability is achieved by feeding an external reference into the internal phase-locked loop (PLL). We report the noise characterization of the internal PLL of Red-Pitaya platform, an open-source embedded system architected around the Zynq 7010 System on Chip, with analog-to-digital and digital-to-analog converters. Our experiments show that, providing an external 10-MHz reference, the PLL exhibits a residual frequency stability of 1.2×10-12 at 1 s and 1.3×10-15 at 4000 s, Allan deviation in 5-Hz bandwidth. These results help to predict the PLL stability as a function of frequency and power of the external reference, and provide guidelines for the design of precision instrumentation, chiefly intended for time and frequency metrology.